Deserialization in PHY - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)

Document ID
PG388
Release Date
2022-05-16
Version
1.0 English

After internal calibration in the PHY is complete, the PHY converts the single-bit data into 8-bit parallel data for each RX lane independently. This 8-bit data is then passed to calibration logic.