| LogiCORE™ IP Facts Table | |
|---|---|
| Core or Subsystem Specifics | |
| Supported Device Family 1 |
Versal® ACAP |
| Supported User Interfaces |
N/A |
| Provided with Core | |
| Design Files |
RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
XDC |
| Simulation Model |
N/A |
| Supported S/W Driver |
N/A |
| Tested Design Flows 2 | |
| Design Entry |
Vivado Design Suite |
| Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
| Synthesis | Vivado Synthesis |
| Support | |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Xilinx Support web page | |
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