- Open the IP Example Design.
- Under Flow Navigator, select Simulation
Settings.
- Select Verilog Compiler Simulator (VCS) as the Target
simulator.
- Browse to the compiled libraries location and set the path
for the Compiled libraries location.
- Under the Simulation tab, set the vcs.simulate.runtime to 1
ms (there are simulation RTL directives which stop the simulation after
certain period of time, which is less than 1 ms) as shown in the following
figure. The Generate simulation scripts only option
generates simulation scripts only. To run behavioral simulation, Generate
simulation scripts only option must be de-selected.
- Apply the settings and select OK.
- In the Flow Navigator window, select Run Simulation
and Run Behavioral Simulation as shown:
- Vivado invokes VCS and simulations are run in the VCS tool. For more
information, see the
Vivado Design Suite User Guide: Logic
Simulation (UG900).