Project Based Simulation Flow Using VCS - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)

Document ID
PG388
Release Date
2022-05-16
Version
1.0 English
  1. Open the IP Example Design.
  2. Under Flow Navigator, select Simulation Settings.
  3.  Select Verilog Compiler Simulator (VCS) as the Target simulator. 
    1. Browse to the compiled libraries location and set the path for the Compiled libraries location.
    2. Under the Simulation tab, set the vcs.simulate.runtime to 1 ms (there are simulation RTL directives which stop the simulation after certain period of time, which is less than 1 ms) as shown in the following figure. The Generate simulation scripts only option generates simulation scripts only. To run behavioral simulation, Generate simulation scripts only option must be de-selected.
  4. Apply the settings and select OK

  5. In the Flow Navigator window, select Run Simulation and Run Behavioral Simulation as shown:

  6. Vivado invokes VCS and simulations are run in the VCS tool. For more information, see the Vivado Design Suite User Guide: Logic Simulation (UG900).