Simulating the Example Design - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)

Document ID
PG388
Release Date
2022-05-16
Version
1.0 English

The example design provides a synthesizable test bench to generate a PRBS data pattern to test TX and RX. In this testbench, for RX, a PRBS pattern will be generated at RX IOs. PRBS generation at RX IOs is non-synthesizable dummy logic. The same pattern will be checked at the user interface. For TX, PRBS will be generated at user interface. The same pattern will be checked at TX IOs. PRBS pattern checking at TX IOs would be non-synthesizable dummy logic. If there are any mismatches between sending and receiving, the pattern error will be flagged. Simulation will be run for 100 transactions for each lane for both TX and RX. The example design can be simulated using one of the methods in the following sections.