The TX interface signals are externally connected to the DAC from the Versal ACAP. These are described in the following table.
| Port Direction | Port Name | Port Description |
|---|---|---|
| Output | TX_D[M-1:0] | TX Data output from XPHY for Single Ended IO Designs |
| Output | TX_D_P[M-1:0] | TX Data output from XPHY for Single Ended IO Designs (P lane of Differential) |
| Output | TX_D_N[M-1:0] | TX Data output from XPHY for Single Ended IO Designs (N lane of Differential) |
| Output | TX_CLK_P, TX_CLK_N | TX clock output from XPHY. |