TX_D_P[M-1:0],TX_D_N[M-1:0] - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)

Document ID
PG388
Release Date
2022-05-16
Version
1.0 English

This output denotes the serialized data of TX lanes. This output is valid only after TX_CLK_P, TX_CLK_N starts toggling. This port exists for differential IO-based designs only.