User Interface - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)

Document ID
PG388
Release Date
2022-05-16
Version
1.0 English

The user interface signals are connected to a Versal ACAP user design. These are described in the following table.

Table 1. User Interface Signals
Port Direction Port Name Port Description
Output app_tx_clk TX Frame clock output to application from IP
Output app_rx_clk RX Frame clock output to application from IP
Input app_rst Reset from Application to IP
Output app_rx_data[N*M -1] RX output data to the Application for each lane. Here 'N' denotes the RX deserialization ratio. N could be 12,14 or 16 as configured by user in the GUI. Here ‘M’ denotes the Number of RX lanes
Output app_rx_valid[M-1] RX output data valid per lane to the Application. Here ‘M’ denotes the Number of RX lanes. This indicates that calibration is done for that particular lane and data is valid for that lane
Input app_tx_data[N*P-1] TX input data from the application for each TX labe. Here 'N' denotes the TX serialization ratio. Here ‘P’ denotes the number of TX lanes
Output app_tx_rdy[P-1] Data ready for each TX lane to the Application. This signal indicates that IP is ready for receiving data from application. Here ‘P’ denotes the Number of TX lanes