app_tx_rdy[P-1] - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)

Document ID
PG388
Release Date
2022-05-16
Version
1.0 English

This output indicates data ready for each TX lane to the application. This signal indicates that the IP is ready to receive data from the application. Here ā€˜Pā€™ denotes the Number of TX lanes.