| Core
Specifics |
| Supported Device Family |
Versal®
AI Core Series
|
| Supported User Interfaces |
AXI4-Lite, AXI4-Stream, memory mapped AXI4
|
| Resources |
See Resource Utilization
|
| Provided with
Core |
| Design Files |
Encrypted RTL and Encrypted AI Engine kernel code |
| Example Design |
Verilog |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Constraints File |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
Included in PetaLinux |
| Tested Design Flows
1
|
| Design Entry |
Vitis™
Unified Software Platform |
| Simulation |
N/A |
| Synthesis |
Vivado®
Synthesis |
| Support |
|
Xilinx
Support web page
|
- For the supported versions of third-party
tools, see the
Vitis
Unified Software Platform Documentation: Application
Acceleration Development (UG1393).
- The DPU is driven by instructions generated by the Vitis AI compiler. When the target neural network
(NN) or DPU hardware architecture is changed, the related .xmodel file that
contains these instructions must be regenerated with the updated arch.json file.
- The DPU does not support the
hw_emu function. The reasons are as follows:
- The RTL code of DPU is encrypted. The Vitis tool does not analyze the source
code.
- The DPU is a co-processor and requires a highly complex
test environment for adequate design verification.
|