DPUCVDX8G has the following ports.
Port Name | Interface Type | Data Width | I/O | Description |
---|---|---|---|---|
m_axi_aclk | Clock | 1 | I | Input clock used for DPUCVDX8G general logic. |
m_axi_aresetn | Reset | 1 | I | Active-Low reset for DPUCVDX8G general logic. |
s_axi_aclk | Clock | 1 | I | AXI clock input for S_AXI_CONTROL. |
s_axi_aresetn | Reset | 1 | I | Active-Low reset for S_AXI_CONTROL. |
interrupt | Interrupt | 1 | O | Active-High interrupt output from the DPUCVDX8G. |
S_AXI_CONTROL | AXI4-Lite | 32 | I/O | 32-bit AXI4-Lite interface for the DPUCVDX8G registers. |
Sxx_OFM_AXIS | AXI4-Stream | 64 | I | Output token data from the AI Engine side to the PL side. The port number depends on the DPUCVDX8G architecture and the batch number. |
Mxx_IFM_AXIS | AXI4-Stream | 128 | O | Input feature map or Weights data from the PL side to the AI Engine side. The port number depends on the DPUCVDX8G architecture and batch number. |
Mxx_WGT_AXIS | AXI4-Stream | 128 | O | Weights data from the PL side to the AI Engine side. The port number depends on the DPUCVDX8G architecture and batch number. |
M00_INSTR_AXI | AXI4 | 32 | I/O | 32-bit memory mapped AXI interface for DPU instructions. |
M00_BIAS_AXI | AXI4 | 128 | I/O | 128-bit memory mapped AXI interface forloading bias data. |
Mxx_IMG_AXI | AXI4 | 128 | I/O | 128-bit memory mapped AXI interface for loading image and uploading output. The port number depends on the DPUCVDX8G architecture and batch number. |
Mxx_WGT_AXI | AXI4 | 512 | I/O | 512-bit memory mapped AXI interface for loading shared weights. The port number is fixed at four. |