Example Design - 1.1 English

Video Warp Processor LogiCORE IP Product Guide (PG396)

Document ID
PG396
Release Date
2022-05-11
Version
1.1 English

Warp Processor is a memory based IP. In this example design the Warp Initializer generates the Warp Filter Parameters for a distortion selected by the user and writes it to the memory. After getting the interrupt from the Warp Initializer, the Warp Filter reads the source image and Warp Filter Parameters from the memory, and writes the distorted image back to memory at the destination address. The Filter IP then generates a frame done interrupt that is connected to the Zynq® UltraScale+™ MPSoC.

The application code programs the distortion parameters that the user provides into the hardware registers of the Warp Initializer and starts the IP. The Warp Initializer writes the Warp Filter Parameters to the memory and generates an interrupt. On receiving the interrupt, the application code programs the input video parameters to the Warp Filter and starts the IP. The Filter IP reads the source image data and Warp Filter Parameters, does interpolation, and writes the output to the destination buffer.

Figure 1. Warp Processor Block Diagram

This chapter provides an example system that includes the Warp Initializer and Warp Filter IPs. Important system-level aspects when designing with the Warp processor IPs are highlighted in these example designs, including the following:

  • Typical usage of the Warp Initializer and the Warp Filter IPs in conjunction with other cores. usage with memory mapped AXI4 interface memory buffers.
  • Usage with memory mapped AXI4 interface memory buffers
  • Configuration of both the IPs by programming the registers.

The supported platforms are listed in the following table.

Table 1. Supported Platforms
Development Boards Additional Hardware Processor
ZCU102 N/A psu_cortexa53_0

To open the example project, perform the following:

  1. Select the Warp Initializer IP and Warp Filter IP from the Vivado IP catalog.
  2. Double-click the selected IP or right-click the IP and select Customize IP from the menu.
  3. Configure the build-time parameters in the Customize IP window and click OK. The Vivado IDE generates an example design matching the build-time configuration.
  4. In the Generate Output Products window, select Generate or Skip. If Generate is selected, the IP output products are generated after a brief moment.
  5. Right-click on either Warp Initializer IP or Warp Filter IP in the Sources panel and select Open IP Example Design from the menu.
  6. In the Open IP Example Design window, select example project directory, and click OK.

The Vivado software then runs automation to generate the example design in the selected directory. The generated project contains a synthesizable example design. Synthesizable example block design, along with top-level file, resides in the Design Sources catalog.