IP Facts - 1.1 English

Video Warp Processor LogiCORE IP Product Guide (PG396)

Document ID
PG396
Release Date
2022-05-11
Version
1.1 English
LogiCORE IP Facts Table
Core Specifics
Supported Device Family 1 UltraScale+™ , UltraScale™ , 7 series FPGAs, Zynq®-7000 SoC Versal® ACAP
Supported User Interfaces AXI Master Lite, AXI4-Lite
Resources

Performance and Resource Use web page for Warp Filter IP

Performance and Resource Use web page for Warp Initializer IP

Provided with Core
Design Files Not Provided
Example Design Verilog
Test Bench Not Provided
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Encrypted RTL
Supported S/W Driver 2

Standalone

Tested Design Flows 3
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 76221
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. Standalone driver details can be found in <install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers_api_toc.htm.
  3. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.