Memory Mapped AXI4 Interface - 1.1 English

Video Warp Processor LogiCORE IP Product Guide (PG396)

Document ID
PG396
Release Date
2022-05-11
Version
1.1 English
There is a memory mapped AXI4 interface named m_axi_mm_video in the Warp Initializer. Warp Filter can be configured with various levels of performance, i.e., Performance Level 0 and 1. In Warp Filter, based on the Performance Level selected in the IP Configuration tab, the number of memory mapped AXI4 interfaces will change. For Performance Level 0, only two memory mapped AXI4 interfaces, named m_axi_mm_video_read and m_axi_mm_video_write are added to the Warp Filter. For Performance Level 1, two more memory mapped AXI4 interfaces named m_axi_mm_video_read1 and m_axi_mm_video_write1 are added to the Warp Filter. The memory mapped AXI4 interfaces run on the ap_clk clock domain. The signals follow the specification as defined in Vivado Design Suite: AXI Reference Guide (UG1037).