The core interfaces are shown in the following figures.
Figure 1. Core Ports
Common Interface Signals
|ap_clk||I||1||Video core clock|
|ap_rst_n||I||1||Video core active-Low clock enable|
|interrupt||O||1||Interrupt Request Pin|
ap_rst_n signals are
shared between the core, memory mapped AXI4 data
interfaces, and the AXI4-Lite control interface.
- The memory mapped AXI4, and
AXI4-Lite interfaces must be synchronous to the
core clock signal ap_clk. All memory mapped AXI4
interface input signals and AXI4-Lite control
interface input signals are sampled on the rising edge of
ap_rst_npin is an active-Low, synchronous reset input pertaining to both AXI4-Lite and memory mapped AXI4 interfaces. When
ap_rst_nis set to 0, the core resets at the next rising edge of
- The interrupt status output bus can be integrated with an external interrupt controller that has independent interrupt enable mask, interrupt clear, and interrupt status registers that allow interrupt aggregation to the system processor.