Register Address Space for Initializer IP - 1.1 English

Video Warp Processor LogiCORE IP Product Guide (PG396)

Document ID
PG396
Release Date
2022-05-11
Version
1.1 English

The Warp Initializer and Warp Filter have specific registers that allow you to control the operation of the core. All registers have an initial value of 0.

The following table provides a detailed description of all the registers that apply globally to the IP.

Table 1. Register Address Space for Warp Initializer
Address (hex) BASEADDR+ Register Name Access Type Register Description
0x0000 Control Signals R/W Bit[0] = ap_start (R/W/COH) 2
Bit[1] = ap_done (R/COR) 3
Bit[2] = ap_idle (R)
Bit[3] = ap_ready (R)
Bit[7] = auto_restart (R/W)
Others = Reserved
0x00004 Global Interrupt Enable R/W Bit[0] = Global interrupt enable
Others = Reserved
0x00008 IP Interrupt Enable R/W Bit[0] = ap_done
Bit[1] = ap_ready
Others = reserved
0x0000C IP Interrupt Status Register R/TOW 1 Bit[0] = ap_done
Bit[1] = ap_ready
Others = Reserved
0x00010 Descriptor Address Register 0 R/W Bit[31] to Bit[0] = LSB 32 bits of the descriptor address
0x00014 Descriptor Address Register 1 R/W Bit[31] to Bit[0] = MSB 32 bits of the descriptor address
0x00020 MAXI Control Address Register R/W Bit[31] to Bit[0] = The user needs to program 0 into this register
  1. TOW- Toggle On Write
  2. COH- Clear on Handshake
  3. COR- Clear on Read
  4. Control Register (0x0000), Global Interrupt Enable Register (0x0004), IP Interrupt Enable Register (0x0008), and IP Interrupt Status Register (0x000C) are explained in section "S_AXILITE Control Register Map" of UG1399. In UG1399, these registers definitions may have some additional bits; however, in this IP, we are accessing only bits mentioned in Table 1. Therefore, only these bits need to be considered while accessing the Control Register, Global Interrupt Enable Register, IP Interrupt Enable Register, and IP Interrupt Status Register.

Registers Description

Control (0x00000) Register
This register controls the operation of the Warp Initializer. Bit[0] of the Control register, ap_start, kicks off the core from software. Writing 1 to this bit starts the core.

Bit[1] of the Control register, ap_done, indicates when the IP has completed all operations in the current transaction. A logic 1 on this signal indicates that the IP has completed all operations in this transaction.

Bit[2] of the Control register, ap_idle, signal indicates if the IP is operating or idle (no operation). The idle state is indicated by logic 1. This signal is asserted low once the IP starts operating. This signal is asserted high when the IP completes operation and no further operations are performed.

Bit[3] of the Control register,ap_ready, signal indicates when the IP is ready for new inputs. It is set to logic 1 when the IP is ready to accept new inputs, indicating that all input reads for this transaction are completed. If the IP has no operations in the pipeline, new reads are not performed until the next transaction starts. This signal is used to make a decision on when to apply new values to the input ports and whether to start a new transaction. Bit[3] to Bit[6] are not used.

Bit[7] of the Control register,auto_restart, can be set to enable the auto-restart mode and then the IP restarts automatically at the end of each transaction.

Global Interrupt Enable (0x00004) Register
This register is the master control for all interrupts. Bit[0] can be used to enable or disable all core interrupts.
IP Interrupt Enable (0x00008) Register
This register allows to selectively enable interrupts. Currently, two interrupt sources are available: ap_done and ap_ready. ap_done is triggered after the frame processing is complete, and ap_ready is triggered after the core is ready to start processing the next frame.
IP Interrupt Status (0x0000C) Register
This is a dual purpose register. When an interrupt occurs, the corresponding interrupt source bit is set in this register. In the readback mode (Get status), the interrupting source can be determined. In the writeback mode (Clear interrupt), the requested interrupt source bit is cleared.
IP Descriptor Address Register 0 (0x00010) Register
This register allows to configure the LSB 32-bit of the 64-bit descriptor address to the IP.
IP Descriptor Address Register 0 (0x00014) Register
This register allows to configure the MSB 32-bit of the 64-bit descriptor address to the IP.
IP MAXI Control Address (0x00020) Register
This register is Warp Initializer Control address into which the user needs to program 0.