Synthesizable Example Design - 1.1 English

Video Warp Processor LogiCORE IP Product Guide (PG396)

Document ID
PG396
Release Date
2022-05-11
Version
1.1 English
The Synthesizable design uses the Zynq UltraScale+ MPSoC microprocessor as AXI4 master. The interrupt port of the Warp Initializer IP and the Warp Filter IP is connected to the Zynq UltraScale+ MPSoC. The Filter IP sends the interrupt after generating the corrected output.
Figure 1. Synthesizable Example Design

The synthesizable example design requires both Vivado® and Vitis™ tools.

The first step is to run synthesis, implementation and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware.

In the window, select Include bitstream, select an export directory and click OK.

The remaining work is performed in the Vitis tool. The Warp processor example design file can be found in the following Vitis directory: /data/embeddedsw/XilinxProcessorIPLib/ drivers/v_warp_filter/examples/

The example application design source files (contained within examples folder) are tightly coupled with the example design available in Vivado IP catalog.

Later, perform the following steps to run the software application:

Important: Make sure that the hardware is powered on and a Digilent Cable or a USB Platform Cable is connected to the host PC. Also, ensure that a USB cable is connected to the UART port of the ZCU102 board.

The example design test results are shown in terminal program.

When executed on the board, the operations are listed in readme.txt in the examples folder. The video input tested are 1080p and 720p.