The synthesizable design uses the Zynq UltraScale+ MPSoC microprocessor as AXI4 master. The interrupt port of the Warp Initializer IP and the Warp Filter IP is connected to the Zynq UltraScale+ MPSoC. The Warp Filter IP sends the interrupt after generating the corrected output.
The synthesizable example design requires both AMD Vivado™ and AMD Vitis™ tools.
The first step is to run synthesis, implementation, and bitstream generation in Vivado. After all those steps are done, select .
In the window, select Include bitstream, select an export directory, and click OK.
The remaining work is performed in the Vitis tool. The Warp Processor example design file can be found in the following Vitis directory: /data/embeddedsw/XilinxProcessorIPLib/ drivers/v_warp_filter/examples/.
The example application design source files (contained within the examples folder) are tightly coupled with the example design available in the Vivado IP catalog.
Later, perform the following steps to run the software application:
The example design test results are shown in the terminal program.
When executed on the board, the operations are listed in readme.txt in the examples folder. The video inputs tested are 1080p and 720p.