This appendix provides details about how this IP core was tested for compliance with the protocol to which it was designed.
A highly parameterizable test bench was used to test both Warp Initializer IP and Warp Filter IP in Vitis™ High- Level Synthesis (HLS) tool. Testing included the following:
- Register accesses
- Processing multiple frames of data
- Varying IP throughput and pixel data width
- Testing of various frame sizes
- Varying parameter settings
- Generating multiple outputs
The Warp Processor IPs has been validated at Xilinx to represent many different parameterizations. A test design was developed for the core that incorporated a Zynq UltraScale+ MPSoC processor, AXI4-Lite interconnect, and various other peripherals. The Zynq UltraScale+ MPSoC processor is responsible for the following functions:
- Programing the IP registers.
- Launching the test.
- Reporting the Pass/Fail status of the test and any errors that were found.