Verification, Compliance, and Interoperability - 1.1 English

Video Warp Processor LogiCORE IP Product Guide (PG396)

Document ID
PG396
Release Date
2022-05-11
Version
1.1 English

This appendix provides details about how this IP core was tested for compliance with the protocol to which it was designed.

Simulation

A highly parameterizable test bench was used to test both Warp Initializer IP and Warp Filter IP in Vitis™ High- Level Synthesis (HLS) tool. Testing included the following:

  1. Register accesses
  2. Processing multiple frames of data
  3. Varying IP throughput and pixel data width
  4. Testing of various frame sizes
  5. Varying parameter settings
  6. Generating multiple outputs

Hardware Testing

The Warp Processor IPs has been validated at Xilinx to represent many different parameterizations. A test design was developed for the core that incorporated a Zynq UltraScale+ MPSoC processor, AXI4-Lite interconnect, and various other peripherals. The Zynq UltraScale+ MPSoC processor is responsible for the following functions:

  1. Programing the IP registers.
  2. Launching the test.
  3. Reporting the Pass/Fail status of the test and any errors that were found.