Clocking - 2.0 English

Versal Adaptive SoC GT Controller for DisplayPort and SDI LogiCORE IP Product Guide (PG398)

Document ID
PG398
Release Date
2023-05-20
Version
2.0 English

The following clocks are used in Versal™ Adaptive SoC GT Controller for DisplayPort and SDI IP for DisplayPort and UHD-SDI:

Table 1. Clocks
Clock I/O Description
gt_ctrl_aclk I Free running clock that is used to bring up the AMD Versal™ device GT and to clock GT helper blocks.
gt_txusrclk I TXUSRCLK2 of master transceiver channel.
gt_rxusrclk I RXUSRCLK2 of master transceiver channel.
clk_100mhz I 100 MHz clock used for UHD-SDI operations.

For more information on clocking, see Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).