The following clocks are used in Versal ACAP GT Controller for DisplayPort and SDI IP for DisplayPort and UHD-SDI:
| Clock | I/O | Description |
|---|---|---|
gt_ctrl_aclk
|
I | Free running clock that is used to bring up the Versal® device GT and to clock GT helper blocks. |
gt_txusrclk
|
I | TXUSRCLK2 of master transceiver channel. |
gt_rxusrclk
|
I | RXUSRCLK2 of master transceiver channel. |
clk_100mhz
|
I | 100 Mhz clock used for UHD-SDI operations. |
For more information on clocking, see Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002).