Constraining the Core - 2.0 English

Versal Adaptive SoC GT Controller for DisplayPort and SDI LogiCORE IP Product Guide (PG398)
Document ID
PG398
Release Date
2023-05-20
Version
2.0 English

Required Constraints

This section defines the additional constraint requirements for the core. Constraints are provided with a Xilinx Design Constraints (XDC) file. The XDC file is provided with the HDL example design to give a starting point for constraints in your design.

Device, Package, and Speed Grade Selections

This section is not applicable for this IP core.

Clock Frequencies

drpclk_in should be specified using the following command: 
create_clock -name gt_ctrl_aclk -period 10.000 [get_ports gt_ctrl_aclk]
This constraint defines the frequency of gt_ctrl_aclk that is supplied to DRP control logic and connected to DRPCLK of GT CHANNEL primitive.
clk_100mhz should be specified using the following command which is only specified in case SDI protocol is used:

create_clock -period 10 [get_ports clk_100mhz]
This constraint defines the frequency of clk_100mhz that is supplied to control logic for SDI operations.

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

This section is not applicable for this IP core.

Transceiver Placement

This section is not applicable for this IP core.

I/O Standard and Placement

The IP core generates clock constraints and necessary false path constraints. But it does not constrain GT locations and reference clock locations. See the respective board user guide or board schematics for LOC and add the constraints to the top level XDC file.