Core Overview - 2.0 English

Versal ACAP GT Controller for DisplayPort and SDI LogiCORE IP Product Guide (PG398)

Document ID
PG398
Release Date
2022-10-19
Version
2.0 English

The Versal ACAP GT Controller for DisplayPort and SDI core implements the use of one or more serial transceivers in a Xilinx® Versal® device. See Product Specification for a detailed description of the core.

The information in this section is intended to supplement, not replace, the information in the Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002). This information highlights features and operating requirements of the GTYE5 transceivers that are of particular importance for UHD-SDI applications and DisplayPort applications.

Versal adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. Most importantly, Versal ACAP hardware and software are targeted for programming and optimization by data scientists and software and hardware developers. Versal ACAPs are enabled by a host of tools such as software libraries, IP, middleware, and frameworks to enable all industry-standard design flows.

In the Versal ACAP GT Controller for DisplayPort and SDI core, the naming convention followed for GTY transceiver ports is same as used in the Versal Architecture Transceivers User Guide. This convention is to use only the base name of a port. When the Versal device transceiver wizard is used to create a GTY wizard module, all input port names have a suffix of_in and all outputs have a suffix of _out. For example, when a port named txpllclksel is referred to in this document, the actual name of that port in the GTH/GTY wrapper is txpllclksel_in.