DisplayPort and UHD-SDI Interface Ports - 2.0 English

Versal ACAP GT Controller for DisplayPort and SDI LogiCORE IP Product Guide (PG398)

Document ID
PG398
Release Date
2022-10-19
Version
2.0 English
Table 1. DisplayPort Transmitter Interface
Signal Name  I/O Description
tx_axi4s_ch<n>_tdata[31:0] I Video data input for Lane <n>
tx_axi4s_ch<n>_tuser[11:0] I User data for Lane <n>
tx_axi4s_ch<n>_tvalid I Video data input valid for lane <n>
tx_axi4s_ch<n>_tready O AXI4-Stream tready output for lane <n>
status_sb_tx_tdata[31:0] O Sideband status to DisplayPort
status_sb_tx_tvalid O Sideband status valid to DisplayPort
status_sb_tx_tready I AXI4-Stream tready Input
Table 2. DisplayPort Receiver Interface
Signal Name  I/O  Description
rx_axi4s_ch<n>_tdata[31:0] O Video data output for Lane <n>
rx_axi4s_ch<n>_tuser[11:0] O User data out for Lane <n>
rx_axi4s_ch<n>_tvalid O Video output data valid for lane <n>
rx_axi4s_ch<n>_tready I AXI4-Stream tready output for lane <n>
control_sb_rx_tdata[7:0] I  Sideband control from DisplayPort
control_sb_rx_tvalid I Sideband control valid from DisplayPort
control_sb_rx_tready O AXI4-Stream tready
status_sb_rx_tdata[31:0] O Sideband status signal to DisplayPort
status_sb_rx_tvalid O Sideband status signal to DisplayPort
status_sb_rx_tready I Core Ready
Table 3. UHD-SDI Transmitter Interface
Signal Name  I/O  Description
tx_axi4s_ch<n>_tdata[39:0] I Video data input for Lane <n>
tx_axi4s_ch<n>_tvalid I Video data input valid for lane <n>
tx_axi4s_ch<n>_tready O AXI4-Stream tready output for lane <n>
sdi_ctrl_sb_tx_in[31:0] I  TX Sideband signal information from SDI for transceiver.
  • bit 2-0: tx_mode
  • bit 3: tx_m
  • bit 31-4: 0
sdi_ctrl_sb_tx_in_tvalid I TX Sideband control valid from SDI
sdi_ctrl_sb_tx_in_tready O AXI4-Stream tready Input
sdi_ctrl_sb_tx_out[31:0] O Sideband signal information to transceiver block.
  • bit 2-0: tx_mode
  • bit 3: tx_m
  • bit 31-4: 0
sdi_ctrl_sb_tx_out_tvalid O TX Sideband control signal valid to transceiver
sdi_ctrl_sb_tx_out_tready I Transceiver Ready
gpi_out_tx O Assert when rate change happens. Connect this signal to GPI port of GT QUAD. Refer to Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002) for more details.
gpo_in_tx O Set corresponded GPO ports in response to assertions of GPI ports. Connect this signal to GPO port of GT QUAD. Refer Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002) for more details.
Table 4. UHD-SDI Receiver Interface
Signal Name  I/O  Description
rx_axi4s_ch<n>_tdat[39:0] O Video data output for channel <n>
rx_axi4s_ch<n>_tvalid O Video output data valid for channel <n>
rx_axi4s_ch<n>_tready I AXI4-Stream tready output for channel <n>
sdi_ctrl_sb_rx_in[31:0] I RX Sideband signal information from SDI.
  • bit 2:0: rx_mode
  • bit 3: rx_mode_locked
  • bit 4: rx_level_b_3g
  • bit 5: rx_ce
  • bit 31–6: unused
sdi_ctrl_sb_rx_in_tvalid I RX Sideband control signal valid to GT Bridge.
sdi_ctrl_sb_rx_in_tready O GT Bridge Ready.
sdi_ctrl_sb_rx_out[31:0] O RX Control Sideband signal information to transceiver.
  • bit 2:0: rx_mode
  • bit 3: rx_mode_locked
  • bit 4: rx_level_b_3g
  • bit 5: rx_ce
  • bit 31–6: unused
sdi_ctrl_sb_rx_out_tvalid O RX Sideband control signal valid to transceiver.
sdi_ctrl_sb_rx_out_tready I Transceiver Ready.
Table 5. DisplayPort Control Input Signals (dp_gt_ctrl[31:0])
Bits Desciption
0 Reset signal
2:1 Specifies the rate information
3 To reset the PLL
6:4 Specifies the number of lanes used
12:8 Specifies the vertical swing information (applicable for TX only)
17:13 Specifies the pre-cursor value (applicable for TX only)
22:18 specifies the post-cursor value (applicable for TX only)
30 Issue the data path reset
31 Power on reset
Table 6. SDI Status Output Signals
Bits Description
0 Used in Duplex and RX only mode. If set to 1, indicates that LCPLL has been locked
1 Used in Duplex and RX only mode. If set to 1, indicates that channel 0 RX reset done has been synced
2 Used in Duplex and RX only mode. If set to 1, indicates that RX changes have been applied
3 Used in Duplex and RX only mode. RX fabric reset
4 Used in Duplex and RX only mode. RX modes locked
5 Used in Duplex and RX only mode. If set to 1, indicates that received data is level B
6 Reserved
7 Used in Duplex and RX only mode. Receiver clock enable signal
10:8 Used in Duplex and RX only mode. Receiver Mode information
11 Used in Duplex or TX only mode. If set to 1,indicates that RPLL has been locked
12 Used in Duplex or TX only mode. If set to 1,indicates that channel 0 TX reset done has been synced
13 Used in Duplex or TX only mode. If set to 1,indicates that TX changes have been applied
14 Used in Duplex or TX only mode. Transmitter fabric reset
15 Reserved