Hardware Debug - 2.0 English

Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues. The Vivado® debug feature is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the debug feature for debugging the specific problems.

GT Clocking

• Make sure PLLs are reset before initiating the IP.
• Monitor the PLL LOCK signal.
• Verify that PLL input clock frequency is of expected value.
• It is mandatory to reset the PLL if clock input to PLL is stopped or unstable.
• Make sure to use PLL default settings from the latest GT Wizard IP core based on the target device.
• Measure RXOUTCLK is of expected frequency.
• Make sure RXOUTCLK of the transceiver is the clock driving rx_usrclk, RXUSRCLK, and RXUSRCLK2.
• Monitor RXBUFFSTATUS[2:0] for overflow and underflow errors.

GT Initialization

• GTRXRESETDONE is asserted high after GT completes initialization.
• Make sure GT is not reset during normal operation.
• Follow the recommended GT reset sequence.