Multiple Link SDI Use-cases on Versal - 2.0 English

Versal ACAP GT Controller for DisplayPort and SDI LogiCORE IP Product Guide (PG398)

Document ID
PG398
Release Date
2022-10-19
Version
2.0 English
Figure 1. Transceiver Quad Configuration of GTYE5

The architecture of GTYE5 consists of four PLL's in total for a QUAD out of which two are shared with Upper DUO and the remaining ones are shared with Lower DUO.
Note: The upper two PLL's will not have access to the Lower GT's and vice-versa.

When supporting multiple links of SDI on Versal, there are two possible use-cases listed below with independent rate control for all the SDI Links.

  1. Multiple SDI Links with Independent reference clocks for Tx and Rx
    Figure 2. High Level Block diagram
    Figure 3. Clocking for Four link SDI with Independent TX and RX Reference Clocks

    To support independent reference clocks for TX and RX with independent rate control of all SDI Links, separate PLL is required for each simplex, that is, two PLL's for each SDI Link.

    As there are only two PLL's in a DUO, one link per DUO or two links in a QUAD can be supported.

    However, four links can be supported, provided that all 4xRx links run only Integer (at different rates) using rate grouping feature in GT Wizard. For example- Link 1 RX can be at 1.5G Integer, Link 2 RX can be at 3G Integer, Link 3 RX can be at 6G Integer, and Link 4 RX can be at 12G Integer. Nevertheless, for the same example, two links cannot be at integer and fractional.

    You can select rate grouping option in GT Bridge as shown in the following figure.

    Note: Enable rate grouping feature only when three or four link support per QUAD is required with independent Reference clock for both Tx and Rx for all remaining use-cases. Uncheck this option in GT Bridge.
    Figure 4. Versal ACAP GT Controller for DisplayPort and SDI GUI
    In this case, where we need to support four links with independent reference clocks, we can not run a link in RX in integer and another link of Rx in Fractional rate. See the following example for supported and not supported cases.
    • Supported case
      • Rx0 can be at 12G Integer
      • Rx1 can be at 6G Integer
      • Rx2 can be at 3G Integer
      • Rx3 can be at 1.5G Integer
    • Supported case
      • Rx0 can be at 12G Fractional
      • Rx1 can be at 6G Fractional
      • Rx2 can be at 3G Fractional
      • Rx3 can be at 1.5G Fractional
    • Not Supported case
      • Rx0 can be at 12G Integer
      • Rx1 can be at 6G Fractional
      • Rx2 can be at 3G Integer
      • Rx3 can be at 1.5G Fractional
  2. Multiple SDI Links with Common reference clocks for TX and RX
    Figure 5. High Level Block diagram
    Figure 6. Clocking for Four link SDI with Common TX and RX Reference Clocks

    To support common reference clocks for TX and RX with independent rate control of all SDI Links, use one PLL for Integer and another PLL for Fractional in a DUO. Use internal resources(Dividers and Multipliers) of GT Quad to support all SDI rates independently for each link.

    By using one PLL for integer and another PLL for fractional, all four links per Quad with independent control for each link can be supported. Below is the example of Simplex configuration.

Figure 7. Versal ACAP GT Controller for DisplayPort and SDI GUI