The Versal ACAP GT Controller for DisplayPort and SDI bridge IP is the supported method of configuring and using transceivers with Xilinx® UHD-SDI and DisplayPort Subsystem IPs. The Versal ACAP GT Controller for DisplayPort and SDI core simplifies serial transceiver (GT) use by providing a standardized interface of serial transceiver functions. The functional block diagram of the core is shown in the following figure.
The Versal ACAP GT Controller for DisplayPort and SDI bridge IP (
v_vid_gt_bridge_ip_v2_0) is available in the IP integrator canvas.
A custom design entry is created through a Bridge IP only. It instantiates, configures, and
connects single or multiple GT quad base IPs (
gt_quad_base_v1_0). You can add the Versal ACAP GT Controller for DisplayPort and SDI bridge IP (
v_vid_gt_bridge_ip_v2_0) in the IPI and configure its parameters (
gt_quad_base_v1_0). IP parameters are programmable through (
v_vid_gt_bridge_ip_v2_0) the GUI including number of lanes and
click Block Automation. It instantiates multiple
gt_quad_base_v1_0 based on the number of lanes configured
gt_bridge_ip_v1_0 and makes all the required connections.
For more information, see IP Integrator (IPI) Design Entry for Custom IP. The supported
features in the Bridge IP are:
- Simplex and Duplex configurations.
- Multiple line rate configurations can be naively captured as part of IP customization.
- Up to16 line rates can be configured per channel per direction.
- Configurable lane Support for 1, 2, and 4 Lanes for DisplayPort Subsystem IPs.
- Max line rate configuration up to 8.1 Gb/s for DisplayPort Subsystem IPs.
- RCPLL and LCPLL selection for UHD-SDI Subsystem IPs.