Resets - 2.0 English

Versal Adaptive SoC GT Controller for DisplayPort and SDI LogiCORE IP Product Guide (PG398)

Document ID
PG398
Release Date
2023-05-20
Version
2.0 English

The following reset signals are used in Versal Adaptive SoC GT Controller for DisplayPort and SDI:

Table 1. Reset Signals
Reset Description
gt_ctrl_aresetn Active-Low reset associated with gt_ctrl_aclk.
rx_pll0_reset QPLL0 reset signal, present when the transceiver common is located in the example design and QPLL0 is used as either the transmitter or receiver PLL type.
rx_pll1_reset QPLL1 reset signal, present when the transceiver common is located in the example design and QPLL0 is used as either the transmitter or receiver PLL type.