SDI - 2.0 English

Versal ACAP GT Controller for DisplayPort and SDI LogiCORE IP Product Guide (PG398)

Document ID
PG398
Release Date
2022-10-19
Version
2.0 English

The Versal GTYE5 requires two reference clocks in case of SDI. One of them is 148.5 MHz and the other is 148.5/1.001 MHz clock. The frequency of the chx_rxoutclk and chx_txoutclk depends on the SDI mode and the width of the GTYE5 transceivers depends on rxdata and txdata ports. The architecture of the GTYE5 transceiver fixes this relationship. The following table shows the frequency details of chx_tx/rxoutclk.

Table 1. Clock Frequencies and Clock Enable Requirements
SDI-Mode Active Data Streams RX/TXDATA Bit Width RX/TXOUTCLK Frequency Clock Enable
HD-SDI 2 20 74.25 or 74.25/1.001 MHz 1/1
3G-SDI A 2 20 148.5 or 148.5/1.001 MHz 1/1
3G-SDI B 4 20 148.5 or 148.5/1.001 MHz 2/2
6G-SDI 4 40 148.5 or 148.5/1.001 MHz 1/1
6G-SDI 8 40 148.5 or 148.5/1.001 MHz 2/2
12G-SDI 8 40 297 or 297/1.001 MHz 2/2