DPU Control Registers - 1.0 English

DPUCADF8H for Convolutional Neural Networks Product Guide (PG400)

Document ID
PG400
Release Date
2024-03-15
Version
1.0 English

The DPU control registers are used to start a DPUCADF8H, waiting for the task to finish and then clear DPUCADF8H status. The details of control registers are in the following table.

Table 1. DPU Control Registers
Register Name Address Bits Description
AP_CTRL 0x000 [31:5] Reserved
[4:4] AP Continue
[3:3] AP Ready
[2:2] AP Idle
[1:1] AP Done
[0:0] AP Start
AP_GIER 0x004 [31:1] Reserved
[0:0] Global Interrupt Enable
AP_IER 0x008 [31:2] Reserved
[1:1] AP Ready Interrupt Enable
[0:0] AP Done Interrupt Enable
AP_ISR 0x00C [31:2] Reserved
[1:1] AP Ready Interrupt Status
[0:0] AP Done Interrupt Status