DPUCADF8H Configuration - 1.0 English

DPUCADF8H for Convolutional Neural Networks Product Guide (PG400)

Document ID
PG400
Release Date
2024-03-15
Version
1.0 English

The deep neural network operators and the associated parameters supported by the DPUCADF8H are in the following table.

Table 1. Deep Neural Network Operators and Parameters Supported by DPUCADF8H
Operators Parameters Description
Convolution Kernel Sizes kernel_w: [1, 16]

kernel_h: [1, 16]

Strides stride_w: [1, 8]

stride_h: [1, 8]

Padding pad_w: [0, 15]

pad_h: [0, 15]

Input Size input_channel: [1, 8192]
Output Size Arbitrary
Activation ReLU, PReLU, Leaky ReLU, ReLU6
Dilated Convolution Kernel Sizes kernel_w: [1, 16]

kernel_h: [1, 16]

Strides stride_w: [1]

stride_h: [1]

Padding pad_w: [0, 15]

pad_h: [0, 15]

Input Size input_channel: [1, 8192]
Output Size Arbitrary
Activation ReLU, PReLU, Leaky ReLU, ReLU6
Deconvolution Kernel Sizes kernel_w: [1, 16]

kernel_h: [1, 16]

Strides stride_w:1

stride_h: 1

Padding pad_w: [0, 15]

pad_h: [0, 15]

Input Size input_channel: [1, 8192]
Output Size Arbitrary
Activation ReLU, PReLU, Leaky ReLU, ReLU6
Full Connected Input Size input_channel: [1, 1048576]
Pooling Kernel Sizes kernel_w: [1, 16]

kernel_h: [1, 16]

Strides stride_w: [1, 8]

stride_h: [1, 8]

Padding pad_w: [0, 15]

pad_h: [0, 15]
constraint: The padded values are counted in any case.

Input Size Arbitrary
Type Max, Average

Elementwise-sum

Input Size Arbitrary
Activation ReLU, Leaky ReLU
Data Reorganization Kernel Sizes kernel_w: [1, 16]
Strides stride_w: [1, 8]
Padding pad_left: [0, 15]

pad_right: [0, 15]

Input Size

input_channel: [1, 32]

input_w: [1, 3840]

input_h: [1, 2160]