The following sections describe the development flow on how to use the DPU IP with the Vitis™ IDE:
IP provides different sets of files for users to select different configurations. For more information, see Configuration Options. Each file set includes the following files:
To use the AI Engine design files and RTL files in program logic region, three types of files are provided:
- Contains the compiled AI Engine design graph. For more information, refer to the AI Engine Tools and Flows User Guide (UG1076).
- xo file
- Vitis kernel file that contains the RTL code files used in program logic.
- Connection file
- Contains the AXI4-Stream connection between the AI Engine and program logic design and also the connection between the program logic design and the NoC.
- *.tcl.rel which can help to improve timing and routability
Send all the input files to the
to generate the xclbin. For more information, refer to the
example design on GitHub.