Customizing and Generating the Bitstream Files with the Vitis Software Platform - 1.1 English

DPUCVDX8H for Convolutional Neural Networks LogiCORE IP Product Guide (PG403)

Document ID
PG403
Release Date
2022-06-24
Version
1.1 English

The following sections describe the development flow on how to use the DPU IP with the Vitis™ IDE:

IP provide different sets of files for users to select different configurations. For more information, see Configuration Options. Each file set includes the following files:

Input Files

To use the AI Engine design files and RTL files in program logic region, three types of files are provided:

libadf.a
contains the compiled AI Engine design graph. For more information, refer to the Versal ACAP AI Engine Programming Environment User Guide (UG1076).
xo file
Vitis kernel file which contains the RTL code files used in program logic.
Connection file
contains the AXI4-Stream connection between the AI Engine and program logic design and also the connection between the program logic design and the NoC.

Vitis Flow

Send all the input files to the v++ command to generate the xclbin. For more information, refer to the example design on GitHub.