DPU Control Registers - 1.1 English

DPUCVDX8H for Convolutional Neural Networks LogiCORE IP Product Guide (PG403)

Document ID
PG403
Release Date
2022-06-24
Version
1.1 English

The DPU control registers are used to start a DPU, wait for the task to finish, and then clear the DPU status. The details of control registers are shown in the following table:

Table 1. DPU Control Registers
Register Address Offset Width Type Description
reg_ap_control 0x000 32 r/w

bit 0: ap_start (read/write/clear on handshake)

bit 1: ap_done (read)

bit 2: ap_idle (read)

bit 3: ap_ready (read)

bit 4: ap_continue (read/write/self clear)

others: reserved

Global interrupt enable register (GIER) 0x004 32 r/w

bit 0: global interrupt enable

others: reserved

IP interrupt enable register (IPIER) 0x008 32 r/w

bit 0: channel 0 (ap_done)

bit 1: channel 1 (ap_ready)

others: reserved

IP interrupt status register (IPISR) 0x00c 32 r/w

bit 0: channel 0 (ap_done) (read/toggle on write)

bit 1: channel 1 (ap_ready) (read/toggle on write)

others: reserved

reg_dpu_start 0x010 32 r/w bit [0]: enable DPU to start
reg_finish_clr 0x018 32 r/w bit [0]: clear reg_finish_sts
reg_finish_sts 0x080 32 r

bit [0]: indicate DPU has finished.

The DPU finish signal is also output as DPU interrupt to trigger xdma or custom logic.

The DPU finish is a level and asynchronous signal.