The DPUCVDX8H has the following features:
- One 32-bit AXI slave interface can be connected to NoC or shell design for accessing configuration and status registers.
- One 256-bit AXI master interface connected to NoC for code fetch.
- Four 256-bit AXI master interfaces connected to NoC for model parameters loading.
- 1~8 512-bit AXI master interface connected to NoC for DPUCVDX8H operates its input/output/intermediate feature-map in DRAM.
The following are a few highlights of the DPUCVDX8H functionality:
- Configurable hardware configuration includes: Engine number
- Convolution and deconvolution
- Max pooling
- Average pooling
- ReLU, ReLU6, and Leaky ReLU
- Fully connected layer
- Batch Normalization