I/O Signals - 1.1 English

DPUCVDX8H for Convolutional Neural Networks LogiCORE IP Product Guide (PG403)

Document ID
PG403
Release Date
2022-06-24
Version
1.1 English

The DPU I/O signals are listed and described in the following table.

Table 1. DPU Signal Description
Signal Name Interface Type Width I/O Description
s_axi_control Memory mapped AXI slave interface 32 I/O 32-bit memory mapped AXI interface for registers.
ap_clk Clock 1 I Input clock used for DPU general logic. The range is from 100 MHz to 300 MHz.
ap_clk_2 Clock 1 I Unused
ap_rst_n Reset 1 I Active-Low reset for DPU general logic.
ap_rst_n_2 Reset 1 I Unused
DPU_AXI_I Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU instructions.
DPU_AXI_W0 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU parameters.
DPU_AXI_W1 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU parameters.
DPU_AXI_W2 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU parameters.
DPU_AXI_W3 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU parameters.
DPU_AXI_0 Memory mapped AXI master interface 512 I/O 512-bit memory mapped AXI interface for DPU engine0.
DPU_AXI_1 Memory mapped AXI master interface 512 I/O 512-bit memory mapped AXI interface for DPU engine1.
DPU_AXI_2 Memory mapped AXI master interface 512 I/O 512-bit memory mapped AXI interface for DPU engine2.
DPU_AXI_3 Memory mapped AXI master interface 512 I/O 512-bit memory mapped AXI interface for DPU engine3.
DPU_AXI_4 Memory mapped AXI master interface 512 I/O 512-bit memory mapped AXI interface for DPU engine4.
DPU_AXI_5 Memory mapped AXI master interface 512 I/O 512-bit memory mapped AXI interface for DPU engine5.
DPU_AXI_6 Memory mapped AXI master interface 512 I/O 512-bit memory mapped AXI interface for DPU engine6.
DPU_AXI_7 Memory mapped AXI master interface 512 I/O 512-bit memory mapped AXI interface for DPU engine7.
DPU_AXIS_M_0F_C0R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_0F_C1R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_0F_C2R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_0F_C3R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_0F_C0R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_0F_C1R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_0F_C2R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_0F_C3R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_0W_C0R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C1R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C2R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C3R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C0R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C1R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C2R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C3R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C0R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C1R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C2R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C3R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C0R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C1R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C2R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0W_C3R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_0B_C0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV bias.
DPU_AXIS_M_0B_C1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV bias.
DPU_AXIS_M_0B_C2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV bias.
DPU_AXIS_M_0B_C3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV bias.
DPU_AXIS_S_0F_C0R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_0F_C1R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_0F_C2R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_0F_C3R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_0F_C0R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_0F_C1R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_0F_C2R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_0F_C3R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_0DF_C0R0 Memory mapped AXImaster interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_0DF_C0R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_0DF_C0R2 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_0DF_C0R3 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_0DF_C1R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_0DF_C1R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_0DF_C1R2 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_0DF_C1R3 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_0DW_R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC weights.
DPU_AXIS_M_0DW_R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC weights.
DPU_AXIS_M_0DW_R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC weights.
DPU_AXIS_M_0DW_R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC weights.
DPU_AXIS_M_0DB_R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC bias.
DPU_AXIS_M_0DB_R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC bias.
DPU_AXIS_M_0DB_R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC bias.
DPU_AXIS_M_0DB_R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC bias.
DPU_AXIS_S_0DF_C0R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_0DF_C0R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_0DF_C0R2 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_0DF_C0R3 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_0DF_C1R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_0DF_C1R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_0DF_C1R2 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_0DF_C1R3 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_1F_C0R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_1F_C1R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_1F_C2R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_1F_C3R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_1F_C0R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_1F_C1R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_1F_C2R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_1F_C3R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_1W_C0R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C1R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C2R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C3R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C0R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C1R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C2R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C3R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C0R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C1R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C2R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C3R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C0R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C1R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C2R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1W_C3R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV weights.
DPU_AXIS_M_1B_C0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV bias.
DPU_AXIS_M_1B_C1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV bias.
DPU_AXIS_M_1B_C2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV bias.
DPU_AXIS_M_1B_C3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for CONV bias.
DPU_AXIS_S_1F_C0R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_1F_C1R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_1F_C2R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_1F_C3R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_1F_C0R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_1F_C1R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_1F_C2R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_S_1F_C3R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for CONV feature map.
DPU_AXIS_M_1DF_C0R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_1DF_C0R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_1DF_C0R2 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_1DF_C0R3 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_1DF_C1R0 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_1DF_C1R1 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_1DF_C1R2 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_1DF_C1R3 Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_M_1DW_R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC weights.
DPU_AXIS_M_1DW_R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC weights.
DPU_AXIS_M_1DW_R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC weights.
DPU_AXIS_M_1DW_R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC weights.
DPU_AXIS_M_1DB_R0 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC bias.
DPU_AXIS_M_1DB_R1 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC bias.
DPU_AXIS_M_1DB_R2 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC bias.
DPU_AXIS_M_1DB_R3 Memory mapped AXI master interface 64 I/O 64-bit memory mapped AXI4-Stream interface for DWC bias.
DPU_AXIS_S_1DF_C0R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_1DF_C0R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_1DF_C0R2 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_1DF_C0R3 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_1DF_C1R0 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_1DF_C1R1 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_1DF_C1R2 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
DPU_AXIS_S_1DF_C1R3 Memory mapped AXI slave interface 128 I/O 128-bit memory mapped AXI4-Stream interface for DWC feature map.
interrupt Interrupt 1 O Active-High interrupt output from DPU.
Note: For a detailed connection guide with AI Engine, refer to Development Flow.