AXI4 Interface - 1.0 English

There are no registers to read, but basic functionality is tested by writing data to the LMB memory and then reading it back. Output S_AXI_AWREADY asserts when the write address is used, S_AXI_WREADY asserts when the write data is used, and output S_AXI_BVALID asserts when the write response is valid. Output S_AXI_ARREADY asserts when the read address is used, and output S_AXI_RVALID asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

• The Clk input is connected and toggling.
• The interface is not being held in reset, and Rst is an active-High reset used by both the AXI and the LMB interfaces.
• If the simulation has been run, verify in simulation and/or a Vivado® debugging tool capture that the waveform is correct for accessing the AXI4 interface.