LMB Interface - 1.0 English

To monitor the LMB interface, use the signals M_ABus, M_DBus, M_ReadStrobe, M_AddrStrobe, M_WriteStrobe, M_BE, LMB_ReadDBus, LMB_Ready, and LMB_Wait. When error correction codes are used, also include the signals LMB_CE, and LMB_UE.

The address on M_ABus is valid when output M_AddrStrobe is asserted, which occurs for each beat in a burst on the AXI interface. Output M_WriteStrobe asserts when the corresponding write data is valid. Output M_ReadStrobe asserts when the corresponding data is read from the interface. If the core is unresponsive, ensure that the following conditions are met:

• The Clk input is connected and toggling.
• The interface is not being held in reset, and Rst is an active-High reset used by both the AXI and the LMB interfaces.
• Input LMB_Ready is asserted and input LMB_Wait is deasserted in response to each access initiated by output M_AddrStrobe.

Detailed LMB timing diagrams are provided in the MicroBlaze Processor Reference Guide (UG984).