LMB Interface Ports - 1.0 English

AXI LMB Bridge LogiCORE IP Product Guide (PG408)
Document ID
PG408
Release Date
2022-05-11
Version
1.0 English
Table 1. LMB Interface
Port Name MSB:LSB I/O Clock Description
M_ABus 0:C_ADDR_WIDTH-1 O Clk LMB Address Bus
M_DBus 0:C_DATA_WIDTH-1 O Clk LMB Write Data Bus
M_ReadStrobe   O Clk LMB Read Strobe
M_AddrStrobe   O Clk LMB Address Strobe
M_WriteStrobe   O Clk LMB Write Strobe
M_BE 0:C_DATA_WIDTH/8-1 O Clk LMB Byte Enable Bus
LMB_ReadDBus 0:C_DATA_WIDTH I Clk LMB Read Data Bus
LMB_Ready   I Clk LMB Data Ready
LMB_Wait   I Clk LMB Wait
LMB_CE   I Clk LMB Correctable Error
LMB_UE   I Clk LMB Uncorrectable Error