The Xilinx® Utility Flip-Flop IP core generates an intermediate flip-flop or latch to bring off-chip signals into internal circuits or out from internal circuits. It helps to reduce errors due to Static Timing Analysis. As you transition from custom flows and IP to the Xilinx Vivado® standard flows (for example, block design container (BDC)) and Vivado IP catalog for Versal® platforms, there are some key areas that can be enhanced from the standard offerings.
One such area is the need for an IP integrator utility IP for configurable flip-flops, that is, a register bank. Although IP integrator is often most useful for higher-level functionality and protocol connectivity, it is certain that some lower bit-level connections are necessary. The set of existing IP integrator utility IPs helps (for example, clock buffers, concat and split, logic gates), but what is missing is the flip-flop. Usually needed for timing or SLR crossing and sometimes for isolation or delays, a simple but configurable IP that instantiates a single rank of flip-flops across a variable vector width would be a great addition to the existing features. The scope of this IP would be configurable only to the width of the signal and the behavior/priority of the reset, thereby instantiating the appropriate primitives in the HDL.