The following table describes the clock domains in the VDU core.
|Domain||Max Freq (MHz)||Description|
|Core clock||800||Processing core, most of the logic and memories|
|MCU clock||571||Internal micro controllers|
|AXI Master Port clock||400||
AXI master port for memory access, 128-bit, typically connected to PS AFI-FM (HP) port or to a soft memory controller in the PL
|AXI4-Lite slave port clock||167||
pll_ref_clkis sourced externally to the device, typically by a programmable clock integrated circuit.
- Video decoder blocks work under the
core_clkdomain generated by the DPLL.
- MCU for decoder work under the
MCU_clkdomain generated by the DPLL.
m_axi_dec_aclkis the AXI clock input from the PL for the 128-bit AXI master interfaces for the decoder.
s_axi_lite_aclkis the AXI4-Lite clock from the PL and PS.
m_axi_mcu_aclkis the MCU AXI master clock from the PL.
The following clock frequency requirements must be met while providing clocks from PL:
- The AXI clock for decoder interface is limited to 400 MHz.
- The following ratio requirements need to be met:
s_axi_lite_aclk≤ 2 ×
Refer to Microcontroller Unit Overview for more information on the MCU.
core_clk is generated based on the VDU DPLL.
mcu_clk is generated based on the VDU DPLL.