Clocking and Resets - 1.0 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

Document ID
PG414
Release Date
2022-07-08
Version
1.0 English

The Video Decode Unit (VDU) core supports one clocking topology, the internal phase locked loop (PLL). An internal DPLL drives the high frequency core (800 MHz) and MCU (571 MHz) clocks based on an input reference clock from the programmable logic (PL) or PS. The internal PLL generates a clock for the decoder block.

Note: All AXI clocks are supplied with clocks from external PL sources. These clocks are asynchronous to core decoder block clock. All primary clocks in VDU are asynchronous to each other.

The VDU core is reset under the following conditions:

  • Initially, while the PL is in power-up/configuration mode, the VDU core is held in reset.
  • After the PL is fully configured, a PL based reset signal can be used to reset the VDU for initialization and bring-up. Platform management unit (PMU) in the processing system can drive this reset signal to control the reset state of the VDU.
  • During partial reconfiguration (PR), the VDU block is kept under reset, if it is part of the dynamically reconfigurable module.