Constraining the Core - 1.0 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

Document ID
PG414
Release Date
2022-07-08
Version
1.0 English

The necessary XDC constraints are delivered with the core generation in the Vivado® Design Suite.

Required Constraints

This section is not applicable for this IP core.

Device, Package, and Speed Grade Selections

This section is not applicable for this IP core.

Note: 4K (3840x2160) and below is supported in all speed grades and 4K DCI (4096x2160) requires -2 or -3 speed grade.

Clock Frequencies

There is no restriction for speed grade. All speed grades support the maximum frequency of operation.

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

This section is not applicable for this IP core.

Transceiver Placement

This section is not applicable for this IP core.

I/O Standard and Placement

This section is not applicable for this IP core.