DPLL Overview - 1.0 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

Document ID
PG414
Release Date
2022-07-08
Version
1.0 English

The VDU core uses in-built DPLL for generating the following clocks:

  • VDU Decoder core clock (upto 800 MHz)
  • VDU MCU clock (upto 571 MHz)

The Vivado® wrapper for VDU should handle programming of DPLL to get the required clocks. This programming is static.