The decoder block is designed to process video streams using the H.265 (HEVC) and H.264 (AVC) standards. It provides support for these standards, including support for 8-bit and 10-bit color depth, 4:0:0, 4:2:0, and 4:2:2 chroma formats, up to 4 streams of 4K UHD at 60 Hz performance.
The decoder block efficiently performs video decompression.
The IP hardware has a direct access to the system data bus through a high-bandwidth master interface to transfer video data to and from an external memory.
The IP control software is partitioned into two layers. The VDU Control Software runs on the APU while the MCU firmware runs on an MCU, which is embedded in the hardware IP. The APU communicates with the embedded MCU through a slave interface, that is also connected to the system bus. The IP hardware is controlled by the embedded MCU using a register map to set decoding parameters through an internal peripheral bus.
The VDU block is shown in the following figure.