Decoder Block Overview - 1.0 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

Document ID
PG414
Release Date
2022-07-08
Version
1.0 English

The Decoder block is capable of decompressing HEVC (ISO/IEC 23008-2 High Efficiency Video Coding) and AVC (ISO/IEC 14496-10 Advanced Video Coding) compliant streams. It provides complete support for these standards, including support for 8-bit and 10-bit color depth, Y-only (monochrome), 4:2:0 and 4:2:2 chroma formats, up to four simultaneous instances of 4K UHD at 60 Hz performance. It also contains global registers, an interrupt controller, and a timer.

Each VDU decoder instance is controlled by a microcontroller (MCU) subsystem. A 32-bit AXI4-Lite slave interface is used by the APU to control the MCU. Two 128-bit AXI4 master interfaces are used to move video data and metadata to and from the system memory. A 32-bit AXI4 master interface is used to fetch the MCU software (instruction cache interface) and load/store additional MCU data (data cache interface). VDU applications running on the APU use the Xilinx VDU Control Software library API to interact with the decoder microcontroller. The microcontroller firmware is not user modifiable.

The decoder includes control registers, a bridge unit, and a set of internal memories. The bridge unit manages the request arbitration, burst addresses, and burst lengths for all external memory accesses required by the decoder.