Decoder Block Register Overview - 1.0 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

Document ID
PG414
Release Date
2022-07-08
Version
1.0 English

The following table lists the decoder block registers. For additional information, see the Versal ACAP AI Engine Register Reference (AM015).

Table 1. Per Instance Decoder Registers
Register Name Offset Type Reset Value Description
MCU_RESET 0x9000 Mixed(1) 0x00000000 MCU Subsystem Reset
MCU_RESET_MODE 0x9004 Mixed(1) 0x00000001 MCU Reset Mode
MCU_STA 0x9008 Mixed(1) 0x00000000 MCU Status
MCU_WAKEUP 0x900C Mixed(1) 0x00000000 MCU Wake-up
MCU_ADDR_OFFSET_IC0 0x9010 RW 0x00000000

MCU Instruction Cache

Address Offset 0

MCU_ADDR_OFFSET_IC1 0x9014 RW 0x00000000

MCU Instruction Cache

Address Offset 1

MCU_ADDR_OFFSET_DC0 0x9018 RW 0x00000000

MCU Data Cache Address

Offset 0

MCU_ADDR_OFFSET_DC1 0x901C RW 0x00000000

MCU Data Cache Address

Offset 1

ITC_MCU_IRQ 0x9100 Mixed(1) 0x00000000 MCU Interrupt Trigger
ITC_CPU_IRQ_MSK 0x9104 RW 0x00000000 CPU Interrupt Mask
ITC_CPU_IRQ_CLR 0x9108 Mixed(1) 0x00000000 CPU Interrupt Clear
ITC_CPU_IRQ_STA 0x910C Mixed(1) 0x00000000 CPU Interrupt Status
AXI_BW 0x9204 RW 0x00000000

AXI Bandwidth

Measurement Window

AXI_ADDR_OFFSET_IP 0x9208 RW 0x00000000 Video Data Address Offset
AXI_RBW0 0x9210 RO 0x00000000

AXI Read Bandwidth

Status 0

AXI_RBW1 0x9214 RO 0x00000000

AXI Read Bandwidth

Status 1

AXI_WBW0 0x9218 RO 0x00000000

AXI Write Bandwidth

Status 0

AXI_WBW1 0x921C RO 0x00000000

AXI Write Bandwidth

Status 1

AXI_RBL0 0x9220 RW 0x00000000

AXI Read Bandwidth

Limiter 0

AXI_RBL1 0x9224 RW 0x00000000

AXI Read Bandwidth

Limiter 1

  1. Mixed registers have read only, write only, and read write bits grouped together.
  2. The VDU output streams are stored in the DDR memory and cannot be routed directly to the decoder. Hence, it is required to use the DDR memory with the VDU.