Interfacing the Core with Versal Devices - 2023.2 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)
Document ID
PG414
Release Date
2024-03-29
Version
2023.2 English
To integrate the VDU core into an IP integrator (IPI) block design, follow these steps:
  1. Launch the AMD Vivado™ IDE and create a new project.

  2. Click Next on New Project wizard until you reach the Family Selection window.
  3. Select a target device for the VDU core.

  4. Click Create Block Design.
  5. Click Add IP and type VDU. The following IP appears.

  6. Add VDU to the block design.
  7. Add AMD Versal™ Control, Interfaces, and Processing System (CIPS) IP to the block design as shown.

  8. In Versal CIPS, enable pl1_ref_clk, pl2_ref_clk, pl3_ref_clk, and set the frequencies as 100,100,167 MHz respectively.

  9. Configure Versal CIPS to enable AXI master interfaces, clocking, and PL-PS interrupt signal per your design requirements. The configuration used in this tutorial is displayed below.

  10. Enable PL to PS interrupts IRQ0 [0-3] ports.
  11. Configure the following parameters in GUI of VDU IP. Set number of decoder instances to 4.
  12. Manually make the connections as follows.
    • Connect ‘vdu_host_interrupt0’ of VDU to ‘pl_ps_irq0’ of Versal CIPS.
    • Connect ‘vdu_host_interrupt1’ of VDU to ‘pl_ps_irq1’ of Versal CIPS.
    • Connect ‘vdu_host_interrupt2’ of VDU to ‘pl_ps_irq2’ of Versal CIPS.
    • Connect ‘vdu_host_interrupt3’ of VDU to ‘pl_ps_irq3’ of Versal CIPS.
  13. Add a SmartConnect IP to the block design. In the GUI set no of master interfaces to 2, slave interface to 1, clock inputs to 2.
  14. Then instantiate a Processor System Reset. Connect ‘ext_reset_in’ of proc_sys_reset_0 to ‘pl0_resetn’ of Versal CIPS.
  15. Make the following connections manually:
    • Connect ‘M_AXI_FPD’ interface of Versal CIPS to ‘S00_AXI’ interface of smartconnect_0.
    • Connect ‘pl3_ref_clk’ pin of Versal CIPS to ‘aclk’ pin of smartconnect_0.
    • Connect ‘pl3_ref_clk’ pin of Versal CIPS to ‘s_axi_lite_aclk’ pin of VDU.
    • Connect ‘pl1_ref_clk’ pin of Versal CIPS to ‘ref_clk’ pin of VDU.
    • Connect ‘M00_AXI’ interface of smartconnect_0 to ‘S_AXI_LITE’ interface of VDU.
    • Connect ‘pl3_ref_clk’ pin of Versal CIPS to ‘slowest_sync_clk’ pin of proc_sys_reset_0.
    • Connect ‘peripheral_aresetn’ pin of proc_sys_reset_0 to ‘vdu_resetn’ pin of VDU.
    • Connect ‘interconnect_aresetn’ pin of proc_sys_reset_0 to ‘aresetn’ pin of smartconnect_0.

    The address and description of PL_AXI_FPD can be found in Versal Adaptive SoC Register Reference (AM012). The address is 0xFD360000. The register is used to configure QoS and the FIFO. It is part of the AFIFM Module. The AFIFM Module documentation provides relative addresses and values for fields defining traffic priority and maximum number of read or write commands.

  16. Instantiate a second AXI smart connect IP (smartconnect_1). In the GUI change the number of master interfaces to 1, slave interfaces to 10. Make the following connections:
    • Connect ‘M_AXI_DEC0_0’ interface of VDU to ‘S00_AXI’ interface of smartconnect_1
    • Connect ‘M_AXI_DEC0_1’ interface of VDU to ‘S01_AXI’ interface of smartconnect_1
    • Connect ‘M_AXI_DEC1_0’ interface of VDU to ‘S02_AXI’ interface of smartconnect_1
    • Connect ‘M_AXI_DEC1_1’ interface of VDU to ‘S03_AXI’ interface of smartconnect_1
    • Connect ‘M_AXI_DEC2_0’ interface of VDU to ‘S04_AXI’ interface of smartconnect_1
    • Connect ‘M_AXI_DEC2_1’ interface of VDU to ‘S05_AXI’ interface of smartconnect_1
    • Connect ‘M_AXI_DEC3_0’ interface of VDU to ‘S06_AXI’ interface of smartconnect_1
    • Connect ‘M_AXI_DEC3_1’ interface of VDU to ‘S07_AXI’ interface of smartconnect_1
    • Connect ‘M_AXI_MCU’ interface of VDU to ‘S08_AXI’ interface of smartconnect_1
    • Connect ‘M01_AXI’ interface of smartconnect_0 to ‘S09_AXI’ interface of smartconnect_1
  17. In add IP section instantiate clocking wizard IP. In the GUI enable reset, under optional ports tab and set it as Active Low.
    • In output clocks tab, set ‘clk_out1’ frequency to 400MHz.
    • Connect ‘clk_in1’ pin of clock_wizard_0 to ‘pl2_ref_clk’ pin of Versal CIPS.
    • Connect ‘clk_out1’ pin of clock_wizard_0 to ‘m_axi_mcu_aclk’ and ‘m_axi_dec_aclk’ pins of VDU.
    • Connect ‘clk_out1’ pin of clock_wizard_0 to ‘aclk1’ pin of smartconnect_0.
    • Connect ‘resetn’ pin of clock_wizard_0 to ‘pl0_resetn’ of Versal CIPS.
    • Connect ‘aclk’ pin of smartconnect_1 to ‘clk_out1’ pin of clock_wizard_0.
  18. Add AXI BRAM Controller and Embedded memory generator from add IP section.
    • In GUI set number of slave interfaces to 1, number of BRAM interfaces to 1.
    • Connect BRAM_PORTA of BRAM Controller to BRAM_PORTA of Embedded memory generator.
    • Connect ‘s_axi_aclk’ of axi_bram_ctrl_0 to ‘clk_out1’ of clock_wizard_0.
  19. Manually connect the reset pins of each IP as specified:
    • Instantiate a new processor system reset (proc_sys_reset_1)
    • Connect ‘clk_out1’ of clock_wizard_0 to ‘slowest_sync_clk’ of proc_sys_reset_1.
    • Connect ‘ext_reset_in’ of proc_sys_reset_1 to ‘pl0_resetn’ of Versal CIPS.
    • Connect ‘aresetn’ of smartconnect_1 to ‘interconnect_aresetn’ of proc_sys_reset_1.
    • Connect ‘peripheral_aresetn’ of proc_sys_reset_1 to ‘s_axi_aresetn’ of axi_bram_ctrl_0.
  20. In the Address Editor tab, expand Data address segment and auto assign the addresses. The following table shows an example address editor.

  21. Click Validate Block Design to validate the connections.

  22. Create a top-level Vivado wrapper by right-clicking on Block Design and selecting the Create HDL Wrapper option as shown in the following figure.
  23. Add the constraints file to the project.
  24. Add the constraints file (.xdc) from the board support package if available. If no constraints file is available, several settings must be changed from their default values to enable error free bitstream generation.
  25. As discussed in the Clocking section, all primary clocks in the VDU are asynchronous to each other. Add below clocking constraint:
    • Set_clock_groups -name async_axi_lite_clk_mcu_clk -asynchronous -group clk_pl_3 -group {clk_pl_2 clkout1_primitive}
  26. Click the Run Synthesis, Run Implementation, or the Generate Bitstream option.