MCU Register Overview - 1.0 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

Document ID
PG414
Release Date
2022-07-08
Version
1.0 English

The following table lists the MCU registers. For additional information, see the Versal ACAP AI Engine Register Reference (AM015).

Note:
  1. VDU0 base address is 0xA4020000
  2. VDU1 base address is 0xA4120000
  3. VDU2 base address is 0xA4220000
  4. VDU3 base address is 0xA4320000. MCU registers should read as base_address of respective VDU+offset.
Table 1. MCU Registers
Register Offset Type Reset Value Description
MCU_RESET 0x9000 mixed(1) 0x00000000 MCU Subsystem Reset
MCU_RESET_MODE 0x9004 mixed(1) 0x00000001 MCU Reset Mode
MCU_STA 0x9008 mixed(1) 0x00000000 MCU Status
MCU_WAKEUP 0x900C mixed(1) 0x00000000 MCU Wake-up
MCU_ADDR_OFFSET_IC0 0x9010 RW 0x00000000 MCU Instruction Cache Address Offset 0
MCU_ADDR_OFFSET_IC1 0x9014 RW 0x00000000 MCU Instruction Cache Address Offset 1
MCU_ADDR_OFFSET_DC0 0x9018 RW 0x00000000 MCU Data Cache Address Offset 0
MCU_ADDR_OFFSET_DC1 0x901C RW 0x00000000 MCU Data Cache Address Offset 1
  1. Mixed registers have read only, write only, and read write bits grouped together.