Operating Timing Window Generation - 1.0 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

Document ID
PG414
Release Date
2022-07-08
Version
1.0 English

The VAPM generates measurement parameters based on two user-selected operating modes.

Start/Stop Mode

In this mode, the measurement window is determined by the start/stop bit in VDU_SLCR.APMn_TRG[start_stop] (n=0,1,2,3) bit. A measurement is triggered when the start bit is set from 0 to 1 in this register and it is stopped when this bit is reset from 1 to 0.

Fixed Duration Timing Window

In this mode, a 32-bit counter is used to generate a fixed length measurement window. When the counter reaches the maximum value, it resets to a value specified in the VDU_SLCR.APMn_TIMER (n = 0, 1, 2, 3) register. The measurement is continued until the 32-bit counter reaches the value set in the APMn_TIMER register and a capture pulse is generated to store the measured values in the VDU_SLCR result registers.

The VAPM is capable of doing the following measurements:

AXI Read and Write Transaction Measurement
Two 32-bit registers count number of read and write 128-bit AXI bus cycles transferred in a given timing window. The measured value is transferred to the VDU_SLCR result register when a capture pulse is generated based on the start/stop mode or the fixed duration timing window mode. To compute the number of bytes transferred, VDU_SLCR must be multiplied by 16.
AXI Read and Write Byte Count Measurement
Two 32-bit registers are implemented to count the number of read and write bytes transferred in a given timing window. The register content has to be multiplied by 16 to know the actual byte count transferred across AXI 128- bit master interface. The measured value is transferred to the VDU_SLCR result register when a capture pulse is generated, based on the start/stop mode or fixed duration timing window mode.
AXI Transaction Latency Measurement
Read and write latency can be measured based on AXI master ID. Read latency is defined as AXI read address acknowledged to last read data cycle. Write latency is defined as AXI write address acknowledged to write response handshaking between master and slave. A 13-bit counter is implemented to measure the latency on read and write bus. The timer is used to timestamp an event. The difference in the timestamp between two events is used to calculate the latency.

Latency can be calculated on transaction ID basis. It is possible to select a single ID or all IDs for latency calculation. For additional information, see the Versal ACAP AI Engine Register Reference (AM015).