Register Space - 1.0 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

Document ID
PG414
Release Date
2022-07-08
Version
1.0 English

VDU is a hardened block in the programmable logic. The following table summarizes the soft IP registers. These registers are accessible from the PS through the AXI4-Lite bus.

Note: For multi-stream use case, the registers in the following table represent the blended values that are input in GUI.
Table 1. Soft IP Registers (Video Configuration)
Register Address Offset Width Type Definition Reset Value
Version control 0x0 8 Read only

3:0- Minor revision

7:4- Major revision

0×5

LogiCORE Lock register

0x4 32 Write only

Lock code for VDU LogiCORE space. By default the space is locked.

Unlocked access returns 0 for register reads and writes are ignored

0x7766DF77- unlock VDU register space

0x0- lock VDU register space

0×0
Control register 0x8 4 R/W

0- soft reset to VDU0

1- soft reset to VDU1

2- soft reset to VDU2

3- soft reset to VDU3

0×0
Secure control 0xC 4 R/W

0- Secure/non-secure configuration for VDU0

1- Secure/non-secure configuration for VDU1

2- Secure/non-secure configuration for VDU2

3- Secure/non-secure configuration for VDU3

0×0
SMID control register 0 0x10 10 RW 9:0- SMID for VDU0, DEC0 0×0
SMID control register 1 0x14 10 RW 9:0- SMID for VDU0, DEC1 0×0
SMID control register 2 0x18 10 RW 9:0- SMID for VDU0, MCU 0×0
SMID control register 3 0x1C 10 RW 9:0- SMID for VDU1, DEC0 0×0
SMID control register 4 0x20 10 RW 9:0- SMID for VDU1, DEC1 0×0
SMID control register 5 0x24 10 RW 9:0- SMID for VDU1, MCU 0×0
SMID control register 6 0x28 10 RW 9:0- SMID for VDU2, DEC0 0×0
SMID control register 7 0x2C 10 RW 9:0- SMID for VDU2, DEC1 0×0
SMID control register 8 0x30 10 RW 9:0- SMID for VDU2, MCU 0×0
SMID control register 9 0x34 10 RW

9:0- SMID for VDU3, DEC0

0×0
SMID control register 10 0x38 10 RW 9:0- SMID for VDU3, DEC1 0×0
SMID control register 11 0x4C 10 RW 9:0- SMID for VDU3, MCU 0×0
VDU_DECODER_ENABLE 0x41004 32 RO

1 = Enable

0 = Disable

0×0