The VDU hard block can be held under reset under the following conditions:
- When external reset input
vdu_resetnsignal is asserted.
- During PL configuration.
- When the VDU to PL isolation is not removed.
The VDU reset signal must be asserted for, at least, two clock cycles of the VDU DPLL reference clock (the slowest clock input to the VDU). The VDU registers can be accessed after the reset signal is deasserted.
- If software resets the VDU block in the middle of a frame, use the software to clear the physical memory allocated for the VDU.
- The reset does not need to be asserted between changes to the configuration during run-time through the control software.
vdu_resetnsignal of Versal® VDU should be driven from Processor System Reset Module (
proc_sys_reset) which is driven by any of the 4 PS reset signals.