The state of the VDU during PL
power up and the initialization sequence for the VDU are as follows:
- PL supply, VDU power supply, RAM supply is turned ON. There is no requirement on sequence.
- PMC releases POR pin to the VDU (por_pl_b).
- POR IP kicks off to monitor VDU, PL, and RAM supplies. Once all powers are detected, the IP releases POR reset, which is sent to PMC readback supply status.
- PMC polls for the power status, and deasserts IPOR register after power ramp
is complete.
At this step, Power on Reset to VDU is released (through the AND gate).
- Send VDU enable information through eFUSE.
- PMC removes isolation gasket controls through PCSR bits.
- Once the clocks are stable, deassert INITSTATE.
- It has to be ensured that the reset to VDU is removed only after the clocks are stable.
Note: The VDU clocks are available while the reset is released.
The PL should be configured before releasing the raw reset.
Additional initialization is done by software through programming the VDU core registers after the PL is configured and core is in a reset release state.