AXI4-Lite Control Register Interface Signals - 1.0 English

AXI Endpoint Protection Unit LogiCORE IP Product Guide (PG418)

Document ID: PG418
Release Date: 2022-10-19
Version: 1.0 English

Note: The following signals are optional and are enabled if HAS_S_AXILITE = 1.

Table 1. S_AXI_CTRL Interface and Interrupt Signals
Signal	I/O	Width	Description
s_axi_ctrl_awvalid	I	1	Write Address channel valid
s_axi_ctrl_awready	O	1	Write Address channel ready
s_axi_ctrl_awaddr	I	12	Write Address channel address
s_axi_ctrl_wdata	I	32	Write Data channel data
s_axi_ctl_wstrb	I	4	Write Data channel byte strobes
s_axi_ctrl_wvalid	I	1	Write Data channel valid
s_axi_ctrl_wready	O	1	Write Data channel ready
s_axi_ctrl_arvalid	I	1	Read Address channel valid
s_axi_ctrl_arready	O	1	Read Address channel ready
s_axi_ctrl_araddr	I	12	Read Address channel address
s_axi_ctrl_rvalid	O	1	Read Data channel valid
s_axi_ctrl_rready	I	1	Read Data channel ready
s_axi_ctrl_rdata	O	32	Read Data channel data
s_axi_ctrl_rresp	O	2	Read Data channel response code (0–3)
s_axi_ctrl_bvalid	O	1	Write Response channel valid
s_axi_ctrl_bready	I	1	Write Response channel ready
s_axi_ctrl_bresp	O	2	Write Response channel response code (0–3)
interrupt	O	1	Interrupt output assert/deassert